2023
Ali, Mustafa; Jaiswal, Akhilesh; Roy, Kaushik; “In-memory bit-serial addition system”2023,US Patent 11,669,302.
Jacob, Ajey; Jaiswal, Akhilesh; “Magneto-electric sensor for hardware trojan detection”2023,US Patent App. 17/922,542.
2022
Jaiswal, Akhilesh; Jacob, Ajey Poovannummoottil; “Array of integrated pixel and memory cells for deep in-sensor, in-memory computing”2022,US Patent 11,468,146.
Jaiswal, Akhilesh R; Jacob, Ajey Poovannummoottil; Bian, Yusheng; Rakowski, Michal; “Optical neuro-mimetic devices”2022,US Patent 11,537,866.
Jaiswal, Akhilesh R; Jacob, Ajey Poovannummoottil; Bian, Yusheng; Pritchard, David C; “Image sensor incorporating an array of optically switchable magnetic tunnel junctions”2022,US Patent 11,226,231.
Jaiswal, Akhilesh R; Paul, Bipul C; “Row-wise tracking of reference generation for memory devices”2022,US Patent App. 16/990,441.
Jaiswal, Akhilesh R; Paul, Bipul C; Soss, Steven R; “Non-volatile transistor embedded static random access memory (SRAM) cell”2022,US Patent 11,475,9411
2021
Jaiswal, Akhilesh Ramlaut; Bhargava, Mudit; “Method, system and device for integration of volatile and non-volatile memory bitcells”2021,US Patent 10,971,229.
Jaiswal, Akhilesh Ramlaut; Bhargava, Mudit; “Method, system and device for magnetic memory”2021,US Patent 10,991,406.
Jaiswal, Akhilesh Ramlaut; Bhargava, Mudit; “D-MRAM devices and methods for replicating data and read and write operations”2021,US Patent 10,896,730.
Jaiswal, Akhilesh; Jacob, Ajey Poovannummoottil; Soss, Steven; “MRAM device comprising random access memory (RAM) and embedded read only memory (ROM)”2021,US Patent 10,964,367.
Jaiswal, Akhilesh; Paul, Bipul C; “Low variability reference parameter generation for magnetic random access memory”2021,US Patent 11,120,857.
Jaiswal, Akhilesh; Jacob, Ajey Poovannummoottil; “Integrated pixel and three-terminal non-volatile memory cell and an array of cells for deep in-sensor, in-memory computing”2021,US Patent 11,069,402.
Jaiswal, Akhilesh; Jacob, Ajey Poovannummoottil; “Integrated pixel and two-terminal non-volatile memory cell and an array of cells for deep in-sensor, in-memory computing”2021,US Patent 11,195,580.
Jaiswal, Akhilesh Ramlaut; Bhargava, Mudit; “Method, system and device for integration of volatile and non-volatile memory bitcells”2021,US Patent App. 17/221,670.
Jaiswal, Akhilesh R; Jacob, Ajey Poovannummoottil; Soss, Steven R; “Circuit structure and method for memory storage with memory cell and MRAM stack”2021,US Patent 11,145,348.
Jacob, Ajey Poovannummoottil; Damoulakis, John; Jaiswal, Akhilesh; Shenoy, Devanand Krishna; Rittenbach, Andrew; “Ml-enabled assured microelectronics manufacturing: a technique to mitigate hardware trojan detection”2021,US Patent App. 17/244,183.
2020
Jaiswal, Akhilesh Ramlaut; Agrawal, Amogh; Roy, Kaushik; “Memory device having in-situ in-memory stateful vector logic operation”2020,US Patent 10,802,827.
Jaiswal, Akhilesh Ramlaut; Bhargava, Mudit; “MRAM read and write methods using an incubation delay interval”2020,US Patent 10,593,397.
Jaiswal, Akhilesh Ramlaut; Bhargava, Mudit; Lattimore, George McNeil; “Backup and/or restore of a memory circuit”2020,US Patent 10,854,291.
Jaiswal, Akhilesh Ramlaut; Agrawal, Amogh; Roy, Kaushik; Chakraborty, Indranil; “Multi-bit dot product engine”2020,US Patent 10,825,510.
Jaiswal, Akhilesh Ramlaut; Bhargava, Mudit; “Read and logic operation methods for voltage-divider bit-cell memory devices”2020,US Patent 10,783,957.
2019
Jaiswal, Akhilesh; Jacob, Ajey P; Paul, Bipul C; Taylor, William; Shum, Danny Pak-Chum; “Magneto-resistive memory structures with improved sensing, and associated sensing methods”2019,US Patent 10,515,679.
Jaiswal, Akhilesh R; Jacob, Ajey Poovannummoottil; “Logic-in-memory computations for non-volatile resistive random access memory (RAM) array”2019,US Patent 10,468,084.
Jaiswal, Akhilesh; Jacob, Ajey Poovannummoottil; “Integrated circuits with look up tables, and methods of producing and operating the same”2019,US Patent 10,468,083.
Jacob, Ajey Poovannummoottil; Akhilesh, Jaiswal; “Integrated circuits including magnetic random access memory structures having reduced switching energy barriers for dual bit operation and methods for fabricating the same”2019,US Patent 10,381,406.
Jacob, Ajey Poovannummoottil; Akhilesh, Jaiswal; “Integrated circuits including magnetic random access memory structures having reduced switching energy barriers for differential bit operation and methods for fabricating the same”2019,US Patent 10,468,456.
Paul, Bipul C; Jaiswal, Akhilesh; Jacob, Ajey Poovannummoottil; Taylor, William; Shum, Danny Pak-Chum; “Integrated circuits having memory cells with shared bit lines and shared source lines”2019,US Patent 10,510,392.